%0 Journal Article %1 WEIBRICH2019120 %A Weißbrich, M. %A Gerlach, L. %A Blume, H. %A Najafi, A. %A García-Ortiz, A. %A Payá Vayá, G. %D 2019 %J Integration, the VLSI Journal %K 2019 myown %P 120 - 137 %R https://doi.org/10.1016/j.vlsi.2019.01.002 %T FLINT+: A runtime-configurable emulation-based stochastic timing analysis framework %U http://www.sciencedirect.com/science/article/pii/S0167926017307794 %V 69 %X ASICs for Stochastic Computing conditions are designed for higher energy-efficiency or performance by sacrificing computational accuracy due to intentional circuit timing violations. To optimize the stochastic behavior, iterative timing analysis campaigns have to be carried out for a variety of circuit timing corner cases. However, the application of common event-driven logic simulators usually leads to excessive analysis runtimes, increasing design time for hardware developers. In this paper, a gate-level netlist-oriented FPGA-based timing analysis framework is proposed, offering a runtime-configuration mechanism for emulating different timing corner cases in hardware without requiring multiple FPGA bitstreams. Logic gates are instrumented with a quantization-based delay model and a critical path selection algorithm is used to reduce the FPGA resource overhead. For an exemplary design space exploration of stochastic CORDIC units, speed-up factors of up to 48 for 10 ps or 476 for 100 ps timing quantization are achieved while maintaining timing behavior deviations lower than 1.5% or 4% to timing simulations, respectively.

@article{WEIBRICH2019120, abstract = {ASICs for Stochastic Computing conditions are designed for higher energy-efficiency or performance by sacrificing computational accuracy due to intentional circuit timing violations. To optimize the stochastic behavior, iterative timing analysis campaigns have to be carried out for a variety of circuit timing corner cases. However, the application of common event-driven logic simulators usually leads to excessive analysis runtimes, increasing design time for hardware developers. In this paper, a gate-level netlist-oriented FPGA-based timing analysis framework is proposed, offering a runtime-configuration mechanism for emulating different timing corner cases in hardware without requiring multiple FPGA bitstreams. Logic gates are instrumented with a quantization-based delay model and a critical path selection algorithm is used to reduce the FPGA resource overhead. For an exemplary design space exploration of stochastic CORDIC units, speed-up factors of up to 48 for 10 ps or 476 for 100 ps timing quantization are achieved while maintaining timing behavior deviations lower than 1.5% or 4% to timing simulations, respectively.}, added-at = {2020-01-09T14:11:01.000+0100}, author = {Weißbrich, M. and Gerlach, L. and Blume, H. and Najafi, A. and García-Ortiz, A. and Payá Vayá, G.}, biburl = {https://www.bibsonomy.org/bibtex/2cf9c199b2a12c56243df3f44df63db3e/imsl3s}, description = {FLINT+: A runtime-configurable emulation-based stochastic timing analysis framework - ScienceDirect}, doi = {https://doi.org/10.1016/j.vlsi.2019.01.002}, interhash = {751ebdb386c25e297c979e5b6045921d}, intrahash = {cf9c199b2a12c56243df3f44df63db3e}, issn = {0167-9260}, journal = {Integration, the VLSI Journal}, keywords = {2019 myown}, pages = {120 - 137}, timestamp = {2020-01-09T14:12:10.000+0100}, title = {FLINT+: A runtime-configurable emulation-based stochastic timing analysis framework}, url = {http://www.sciencedirect.com/science/article/pii/S0167926017307794}, volume = 69, year = 2019 }