%0 Journal Article %1 journals/tcad/ChenB01 %A Chen, Yirng-An %A Bryant, Randal E. %D 2001 %J IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. %K dblp %N 12 %P 1443-1454 %T An efficient graph representation for arithmetic circuitverification. %U http://dblp.uni-trier.de/db/journals/tcad/tcad20.html#ChenB01 %V 20

@article{journals/tcad/ChenB01, added-at = {2020-09-24T00:00:00.000+0200}, author = {Chen, Yirng-An and Bryant, Randal E.}, biburl = {https://www.bibsonomy.org/bibtex/2ab11f37ef31023b8dde6276141048907/dblp}, ee = {https://doi.org/10.1109/43.969437}, interhash = {dae743e788b481d5528fd8ea36630042}, intrahash = {ab11f37ef31023b8dde6276141048907}, journal = {IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.}, keywords = {dblp}, number = 12, pages = {1443-1454}, timestamp = {2020-09-25T11:44:44.000+0200}, title = {An efficient graph representation for arithmetic circuitverification.}, url = {http://dblp.uni-trier.de/db/journals/tcad/tcad20.html#ChenB01}, volume = 20, year = 2001 }