%0 Conference Paper %1 Gottschall:2021:TIP %A Gottschall, Björn %A Eeckhout, Lieven %A Jahre, Magnus %B MICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture %D 2021 %I ACM %K Hardware InstructionLevel Profiler Simulation %P 15--27 %R 10.1145/3466752.3480058 %T TIP: Time-Proportional Instruction Profiling %X A fundamental part of developing software is to understand what the application spends time on. This is typically determined using a performance profiler which essentially captures how execution time is distributed across the instructions of a program. At the same time, the highly parallel execution model of modern high-performance processors means that it is difficult to reliably attribute time to instructions — resulting in performance analysis being unnecessarily challenging. In this work, we first propose the Oracle profiler which is a golden reference for performance profilers. Oracle is golden because (i) it accounts every clock cycle and every dynamic instruction, and (ii) it is time-proportional, i.e., it attributes a clock cycle to the instruction(s) that the processor exposes the latency of. We use Oracle to, for the first time, quantify the error of software-level profiling, the dispatch-tagging heuristic used in AMD IBS and Arm SPE, the Last-Committing Instruction (LCI) heuristic used in external monitors, and the Next-Committing Instruction (NCI) heuristic used in Intel PEBS, resulting in average instruction-level profile errors of 61.8%, 53.1%, 55.4%, and 9.3%, respectively. The reason for these errors is that all existing profilers have cases in which they systematically attribute execution time to instructions that are not the root cause of performance loss. To overcome this issue, we propose Time-Proportional Instruction Profiling (TIP) which combines Oracle’s time attribution policies with statistical sampling to enable practical implementation. We implement TIP within the Berkeley Out-of-Order Machine (BOOM) and find that TIP is highly accurate. More specifically, TIP’s instruction-level profile error is only 1.6% on average (maximally 5.0%) versus 9.3% on average (maximally 21.0%) for state-of-the-art NCI. TIP’s improved accuracy matters in practice, as we exemplify by using TIP to identify a performance problem in the SPEC CPU2017 benchmark Imagick that, once addressed, improves performance by 1.93 ×. %@ 9781450385572

@inproceedings{Gottschall:2021:TIP, abstract = {A fundamental part of developing software is to understand what the application spends time on. This is typically determined using a performance profiler which essentially captures how execution time is distributed across the instructions of a program. At the same time, the highly parallel execution model of modern high-performance processors means that it is difficult to reliably attribute time to instructions — resulting in performance analysis being unnecessarily challenging. In this work, we first propose the Oracle profiler which is a golden reference for performance profilers. Oracle is golden because (i) it accounts every clock cycle and every dynamic instruction, and (ii) it is time-proportional, i.e., it attributes a clock cycle to the instruction(s) that the processor exposes the latency of. We use Oracle to, for the first time, quantify the error of software-level profiling, the dispatch-tagging heuristic used in AMD IBS and Arm SPE, the Last-Committing Instruction (LCI) heuristic used in external monitors, and the Next-Committing Instruction (NCI) heuristic used in Intel PEBS, resulting in average instruction-level profile errors of 61.8%, 53.1%, 55.4%, and 9.3%, respectively. The reason for these errors is that all existing profilers have cases in which they systematically attribute execution time to instructions that are not the root cause of performance loss. To overcome this issue, we propose Time-Proportional Instruction Profiling (TIP) which combines Oracle’s time attribution policies with statistical sampling to enable practical implementation. We implement TIP within the Berkeley Out-of-Order Machine (BOOM) and find that TIP is highly accurate. More specifically, TIP’s instruction-level profile error is only 1.6% on average (maximally 5.0%) versus 9.3% on average (maximally 21.0%) for state-of-the-art NCI. TIP’s improved accuracy matters in practice, as we exemplify by using TIP to identify a performance problem in the SPEC CPU2017 benchmark Imagick that, once addressed, improves performance by 1.93 ×.}, added-at = {2024-05-19T23:39:48.000+0200}, author = {Gottschall, Björn and Eeckhout, Lieven and Jahre, Magnus}, biburl = {https://www.bibsonomy.org/bibtex/289d95677b07ea14230cca0304b38a33a/gron}, booktitle = {MICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture}, day = 17, doi = {10.1145/3466752.3480058}, interhash = {1384d15e3dd525c18e5afdf836cad0bf}, intrahash = {89d95677b07ea14230cca0304b38a33a}, isbn = {9781450385572}, keywords = {Hardware InstructionLevel Profiler Simulation}, location = {Virtual Event, Greece}, month = {10}, pages = {15--27}, publisher = {ACM}, series = {MICRO '21}, timestamp = {2024-05-19T23:39:48.000+0200}, title = {TIP: Time-Proportional Instruction Profiling}, year = 2021 }