%0 Thesis %1 phd/it/Solinas09 %A Solinas, Marco %D 2009 %K dblp %T Cache Architectures for Wire-Delay Dominated CMP Systems.

@phdthesis{phd/it/Solinas09, added-at = {2023-05-08T00:00:00.000+0200}, author = {Solinas, Marco}, biburl = {https://www.bibsonomy.org/bibtex/219243ed61c7c440fdbc49a2fc3302a2f/dblp}, ee = {https://opac.bncf.firenze.sbn.it/bncf-prod/resource?uri=TD20015092}, interhash = {7a94e0643be1b8b2cebde60c5abe5150}, intrahash = {19243ed61c7c440fdbc49a2fc3302a2f}, keywords = {dblp}, school = {University of Pisa, Italy}, timestamp = {2024-04-09T09:27:48.000+0200}, title = {Cache Architectures for Wire-Delay Dominated CMP Systems.}, year = 2009 }