%0 Journal Article %1 journals/jssc/AgarwalPMR05 %A Agarwal, Amit %A Paul, Bipul C. %A Mukhopadhyay, Saibal %A Roy, Kaushik %D 2005 %J IEEE J. Solid State Circuits %K dblp %N 9 %P 1804-1814 %T Process variation in embedded memories: failure analysis and variation aware architecture. %U http://dblp.uni-trier.de/db/journals/jssc/jssc40.html#AgarwalPMR05 %V 40

@article{journals/jssc/AgarwalPMR05, added-at = {2022-03-02T00:00:00.000+0100}, author = {Agarwal, Amit and Paul, Bipul C. and Mukhopadhyay, Saibal and Roy, Kaushik}, biburl = {https://www.bibsonomy.org/bibtex/22eb6f5b2711bbec50a49b5b671c07ac8/dblp}, ee = {https://doi.org/10.1109/JSSC.2005.852159}, interhash = {4edb45b1ef12a2feb3f28c3617e36480}, intrahash = {2eb6f5b2711bbec50a49b5b671c07ac8}, journal = {IEEE J. Solid State Circuits}, keywords = {dblp}, number = 9, pages = {1804-1814}, timestamp = {2024-04-08T10:43:31.000+0200}, title = {Process variation in embedded memories: failure analysis and variation aware architecture.}, url = {http://dblp.uni-trier.de/db/journals/jssc/jssc40.html#AgarwalPMR05}, volume = 40, year = 2005 }