%0 Journal Article %1 journals/tcad/PomeranzR05a %A Pomeranz, Irith %A Reddy, Sudhakar M. %D 2005 %J IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. %K dblp %N 8 %P 1271-1274 %T On fault equivalence, fault dominance, and incompletely specified test sets. %U http://dblp.uni-trier.de/db/journals/tcad/tcad24.html#PomeranzR05a %V 24

@article{journals/tcad/PomeranzR05a, added-at = {2020-09-24T00:00:00.000+0200}, author = {Pomeranz, Irith and Reddy, Sudhakar M.}, biburl = {https://www.bibsonomy.org/bibtex/2afe0d1b1aaf5b554e7fb7793c42cd7f4/dblp}, ee = {https://doi.org/10.1109/TCAD.2005.850822}, interhash = {9ae108ef2efee97177eb12b03e5eae48}, intrahash = {afe0d1b1aaf5b554e7fb7793c42cd7f4}, journal = {IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.}, keywords = {dblp}, number = 8, pages = {1271-1274}, timestamp = {2020-09-25T11:47:21.000+0200}, title = {On fault equivalence, fault dominance, and incompletely specified test sets.}, url = {http://dblp.uni-trier.de/db/journals/tcad/tcad24.html#PomeranzR05a}, volume = 24, year = 2005 }