%0 Journal Article %1 journals/tcad/MalikSBS93 %A Malik, Sharad %A Singh, Kanwar Jit %A Brayton, Robert K. %A Sangiovanni-Vincentelli, Alberto L. %D 1993 %J IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. %K dblp %N 5 %P 568-578 %T Performance optimization of pipelined logic circuits using peripheral retiming and resynthesis. %U http://dblp.uni-trier.de/db/journals/tcad/tcad12.html#MalikSBS93 %V 12

@article{journals/tcad/MalikSBS93, added-at = {2023-09-30T00:00:00.000+0200}, author = {Malik, Sharad and Singh, Kanwar Jit and Brayton, Robert K. and Sangiovanni-Vincentelli, Alberto L.}, biburl = {https://www.bibsonomy.org/bibtex/2fd536d87ec0c43d6d7a529a756654ded/dblp}, ee = {https://www.wikidata.org/entity/Q57380961}, interhash = {f1a8223ac320a358a96321b085c19f3b}, intrahash = {fd536d87ec0c43d6d7a529a756654ded}, journal = {IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.}, keywords = {dblp}, number = 5, pages = {568-578}, timestamp = {2024-04-08T19:46:35.000+0200}, title = {Performance optimization of pipelined logic circuits using peripheral retiming and resynthesis.}, url = {http://dblp.uni-trier.de/db/journals/tcad/tcad12.html#MalikSBS93}, volume = 12, year = 1993 }