%0 Journal Article %1 journals/tvlsi/AbbaspourPAK06 %A Abbaspour, Soroush %A Pedram, Massoud %A Ajami, Amir H. %A Kashyap, Chandramouli V. %D 2006 %J IEEE Trans. Very Large Scale Integr. Syst. %K dblp %N 12 %P 1383-1388 %T Fast Interconnect and Gate Timing Analysis for Performance Optimization. %U http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi14.html#AbbaspourPAK06 %V 14

@article{journals/tvlsi/AbbaspourPAK06, added-at = {2020-03-11T00:00:00.000+0100}, author = {Abbaspour, Soroush and Pedram, Massoud and Ajami, Amir H. and Kashyap, Chandramouli V.}, biburl = {https://www.bibsonomy.org/bibtex/2b33d339c903e2b0616a46407f30dd2f2/dblp}, ee = {https://doi.org/10.1109/TVLSI.2006.887834}, interhash = {c378a2eb0de3e4d6e65fcc32d9cebf7e}, intrahash = {b33d339c903e2b0616a46407f30dd2f2}, journal = {IEEE Trans. Very Large Scale Integr. Syst.}, keywords = {dblp}, number = 12, pages = {1383-1388}, timestamp = {2020-03-12T11:45:40.000+0100}, title = {Fast Interconnect and Gate Timing Analysis for Performance Optimization.}, url = {http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi14.html#AbbaspourPAK06}, volume = 14, year = 2006 }