%0 Conference Paper %1 conf/icecsys/ZaatarN00 %A Zaatar, Wadih %A Nasr, George E. %B ICECS %D 2000 %I IEEE %K dblp %P 169-172 %T An implementation scheme for a microprocessor emulator. %U http://dblp.uni-trier.de/db/conf/icecsys/icecsys2000.html#ZaatarN00 %@ 0-7803-6542-9

@inproceedings{conf/icecsys/ZaatarN00, added-at = {2021-01-20T00:00:00.000+0100}, author = {Zaatar, Wadih and Nasr, George E.}, biburl = {https://www.bibsonomy.org/bibtex/21a0e7cec7edd7995ef3c3c716d739a93/dblp}, booktitle = {ICECS}, crossref = {conf/icecsys/2000}, ee = {https://doi.org/10.1109/ICECS.2000.911510}, interhash = {1265a313d42a76b5b8180eddb206642b}, intrahash = {1a0e7cec7edd7995ef3c3c716d739a93}, isbn = {0-7803-6542-9}, keywords = {dblp}, pages = {169-172}, publisher = {IEEE}, timestamp = {2024-04-09T16:20:16.000+0200}, title = {An implementation scheme for a microprocessor emulator.}, url = {http://dblp.uni-trier.de/db/conf/icecsys/icecsys2000.html#ZaatarN00}, year = 2000 }