%0 Conference Paper %1 conf/vlsid/SinghKK96 %A Singh, Jaswinder Pal %A Kumar, Anshul %A Kumar, Shashi %B VLSI Design %D 1996 %I IEEE Computer Society %K dblp %P 322-323 %T A multiplier generator for Xilinx FPGAs. %U http://dblp.uni-trier.de/db/conf/vlsid/vlsid1996.html#SinghKK96 %@ 0-8186-7228-5

@inproceedings{conf/vlsid/SinghKK96, added-at = {2023-03-24T00:00:00.000+0100}, author = {Singh, Jaswinder Pal and Kumar, Anshul and Kumar, Shashi}, biburl = {https://www.bibsonomy.org/bibtex/2d89fe8ced24e2c4c799971160a3c2f36/dblp}, booktitle = {VLSI Design}, crossref = {conf/vlsid/1996}, ee = {https://doi.ieeecomputersociety.org/10.1109/ICVD.1996.489622}, interhash = {12cdf86783c074ff8b7162846265b036}, intrahash = {d89fe8ced24e2c4c799971160a3c2f36}, isbn = {0-8186-7228-5}, keywords = {dblp}, pages = {322-323}, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T05:46:51.000+0200}, title = {A multiplier generator for Xilinx FPGAs.}, url = {http://dblp.uni-trier.de/db/conf/vlsid/vlsid1996.html#SinghKK96}, year = 1996 }