%0 Journal Article %1 journals/ijrc/SinhaS14a %A Sinha, Sharad %A Srikanthan, Thambipillai %D 2014 %J Int. J. Reconfigurable Comput. %K dblp %P 564924:1-564924:14 %T Architecture and Application-Aware Management of Complexity of Mapping Multiplication to FPGA DSP Blocks in High Level Synthesis. %U http://dblp.uni-trier.de/db/journals/ijrc/ijrc2014.html#SinhaS14a %V 2014

@article{journals/ijrc/SinhaS14a, added-at = {2020-04-02T00:00:00.000+0200}, author = {Sinha, Sharad and Srikanthan, Thambipillai}, biburl = {https://www.bibsonomy.org/bibtex/21b43798cc227e50c64895aeea57d226d/dblp}, ee = {https://www.wikidata.org/entity/Q59046546}, interhash = {130e026dcaac6defdae85fa5f984545b}, intrahash = {1b43798cc227e50c64895aeea57d226d}, journal = {Int. J. Reconfigurable Comput.}, keywords = {dblp}, pages = {564924:1-564924:14}, timestamp = {2020-04-03T11:40:46.000+0200}, title = {Architecture and Application-Aware Management of Complexity of Mapping Multiplication to FPGA DSP Blocks in High Level Synthesis.}, url = {http://dblp.uni-trier.de/db/journals/ijrc/ijrc2014.html#SinhaS14a}, volume = 2014, year = 2014 }