%0 Journal Article %1 journals/tcad/SuYZZC17 %A Su, Jincheng %A Yang, Fan %A Zeng, Xuan %A Zhou, Dian %A Chen, Jie %D 2017 %J IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. %K dblp %N 10 %P 1674-1687 %T Efficient Memory Partitioning for Parallel Data Access in FPGA via Data Reuse. %U http://dblp.uni-trier.de/db/journals/tcad/tcad36.html#SuYZZC17 %V 36

@article{journals/tcad/SuYZZC17, added-at = {2020-10-09T00:00:00.000+0200}, author = {Su, Jincheng and Yang, Fan and Zeng, Xuan and Zhou, Dian and Chen, Jie}, biburl = {https://www.bibsonomy.org/bibtex/27a442c3cabd3015e82fdc8a2c7da5bc7/dblp}, ee = {https://doi.org/10.1109/TCAD.2017.2648838}, interhash = {1561d3deb67d3cbae18be9685f0770bd}, intrahash = {7a442c3cabd3015e82fdc8a2c7da5bc7}, journal = {IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.}, keywords = {dblp}, number = 10, pages = {1674-1687}, timestamp = {2020-10-10T11:35:13.000+0200}, title = {Efficient Memory Partitioning for Parallel Data Access in FPGA via Data Reuse.}, url = {http://dblp.uni-trier.de/db/journals/tcad/tcad36.html#SuYZZC17}, volume = 36, year = 2017 }