%0 Journal Article %1 journals/tvlsi/WangWLSZ19 %A Wang, Hang %A Wang, Tiancheng %A Liu, Longjun %A Sun, Hongbin %A Zheng, Nanning %D 2019 %J IEEE Trans. Very Large Scale Integr. Syst. %K dblp %N 10 %P 2423-2433 %T Efficient Compression-Based Line Buffer Design for Image/Video Processing Circuits. %U http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi27.html#WangWLSZ19 %V 27

@article{journals/tvlsi/WangWLSZ19, added-at = {2020-03-11T00:00:00.000+0100}, author = {Wang, Hang and Wang, Tiancheng and Liu, Longjun and Sun, Hongbin and Zheng, Nanning}, biburl = {https://www.bibsonomy.org/bibtex/218b3899035e3ed273c18c21c7dd19031/dblp}, ee = {https://doi.org/10.1109/TVLSI.2019.2921249}, interhash = {25bee3f5726aa56e5a1aa89365b208a8}, intrahash = {18b3899035e3ed273c18c21c7dd19031}, journal = {IEEE Trans. Very Large Scale Integr. Syst.}, keywords = {dblp}, number = 10, pages = {2423-2433}, timestamp = {2020-03-12T11:45:29.000+0100}, title = {Efficient Compression-Based Line Buffer Design for Image/Video Processing Circuits.}, url = {http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi27.html#WangWLSZ19}, volume = 27, year = 2019 }