%0 Journal Article %1 journals/todaes/ChengHKLM23 %A Cheng, Chung-Kuan %A Holtz, Chester %A Kahng, Andrew B. %A Lin, Bill %A Mallappa, Uday %D 2023 %J ACM Trans. Design Autom. Electr. Syst. %K dblp %N 4 %P 52:1-52:31 %T DAGSizer: A Directed Graph Convolutional Network Approach to Discrete Gate Sizing of VLSI Graphs. %U http://dblp.uni-trier.de/db/journals/todaes/todaes28.html#ChengHKLM23 %V 28

@article{journals/todaes/ChengHKLM23, added-at = {2023-08-31T00:00:00.000+0200}, author = {Cheng, Chung-Kuan and Holtz, Chester and Kahng, Andrew B. and Lin, Bill and Mallappa, Uday}, biburl = {https://www.bibsonomy.org/bibtex/282090397e396a54381bd4c9632e3bc83/dblp}, ee = {https://doi.org/10.1145/3577019}, interhash = {27434da798d5369839a726d2993d397f}, intrahash = {82090397e396a54381bd4c9632e3bc83}, journal = {ACM Trans. Design Autom. Electr. Syst.}, keywords = {dblp}, month = {July}, number = 4, pages = {52:1-52:31}, timestamp = {2024-04-08T21:43:00.000+0200}, title = {DAGSizer: A Directed Graph Convolutional Network Approach to Discrete Gate Sizing of VLSI Graphs.}, url = {http://dblp.uni-trier.de/db/journals/todaes/todaes28.html#ChengHKLM23}, volume = 28, year = 2023 }