Inproceedings,
A 0.1-to-1.5GHz 4.2mW All-Digital DLL with Dual Duty-Cycle Correction Circuit and Update Gear Circuit for DRAM in 66nm CMOS Technology.
W. Yun, H. Lee, D. Shin, S. Kang, J. Yang, H. Lee, D. Lee, S. Sim, Y. Kim, W. Choi, K. Song, S. Shin, H. Choi, H. Moon, S. Kwack, J. Lee, Y. Choi, N. Park, K. Kim, Y. Choi, J. Ahn, and Y. Yang.ISSCC, page 282-283. IEEE, (2008)
Meta data
- BibTeX key
- conf/isscc/YunLSKYLLSKCSSCMKLCPKCAY08
- entry type
- inproceedings
- booktitle
- ISSCC
- year
- 2008
- pages
- 282-283
- publisher
- IEEE
- crossref
- conf/isscc/2008
- ee
- http://dx.doi.org/10.1109/ISSCC.2008.4523167
- isbn
- 978-1-4244-2010-0
- url
- http://dblp.uni-trier.de/db/conf/isscc/isscc2008.html#YunLSKYLLSKCSSCMKLCPKCAY08
Tags
Users
Comments and Reviewsshow / hide
Cite this publication
More citation styles
- please select -%0 Conference Paper
%1 conf/isscc/YunLSKYLLSKCSSCMKLCPKCAY08
%A Yun, Won-Joo
%A Lee, Hyun-Woo
%A Shin, Dongsuk
%A Kang, Shin-Deok
%A Yang, Ji-Yeon
%A Lee, Hyeng-Ouk
%A Lee, Dong-Uk
%A Sim, Sujeong
%A Kim, Young-Ju
%A Choi, Won-Jun
%A Song, Keun-Soo
%A Shin, Sang-Hoon
%A Choi, Hyang-Hwa
%A Moon, Hyung-Wook
%A Kwack, Seung-Wook
%A Lee, Jung-Woo
%A Choi, Young-Kyoung
%A Park, Nak-Kyu
%A Kim, Kwan-Weon
%A Choi, Young-Jung
%A Ahn, Jin-Hong
%A Yang, Ye Seok
%B ISSCC
%D 2008
%I IEEE
%K dblp
%P 282-283
%T A 0.1-to-1.5GHz 4.2mW All-Digital DLL with Dual Duty-Cycle Correction Circuit and Update Gear Circuit for DRAM in 66nm CMOS Technology.
%U http://dblp.uni-trier.de/db/conf/isscc/isscc2008.html#YunLSKYLLSKCSSCMKLCPKCAY08
%@ 978-1-4244-2010-0
@inproceedings{conf/isscc/YunLSKYLLSKCSSCMKLCPKCAY08,
added-at = {2015-10-13T00:00:00.000+0200},
author = {Yun, Won-Joo and Lee, Hyun-Woo and Shin, Dongsuk and Kang, Shin-Deok and Yang, Ji-Yeon and Lee, Hyeng-Ouk and Lee, Dong-Uk and Sim, Sujeong and Kim, Young-Ju and Choi, Won-Jun and Song, Keun-Soo and Shin, Sang-Hoon and Choi, Hyang-Hwa and Moon, Hyung-Wook and Kwack, Seung-Wook and Lee, Jung-Woo and Choi, Young-Kyoung and Park, Nak-Kyu and Kim, Kwan-Weon and Choi, Young-Jung and Ahn, Jin-Hong and Yang, Ye Seok},
biburl = {https://www.bibsonomy.org/bibtex/24ee11a0ba7e2c5e791345aab6ed40246/dblp},
booktitle = {ISSCC},
crossref = {conf/isscc/2008},
ee = {http://dx.doi.org/10.1109/ISSCC.2008.4523167},
interhash = {38fa450657240ff6753aa3a6967559a1},
intrahash = {4ee11a0ba7e2c5e791345aab6ed40246},
isbn = {978-1-4244-2010-0},
keywords = {dblp},
pages = {282-283},
publisher = {IEEE},
timestamp = {2015-10-14T11:35:13.000+0200},
title = {A 0.1-to-1.5GHz 4.2mW All-Digital DLL with Dual Duty-Cycle Correction Circuit and Update Gear Circuit for DRAM in 66nm CMOS Technology.},
url = {http://dblp.uni-trier.de/db/conf/isscc/isscc2008.html#YunLSKYLLSKCSSCMKLCPKCAY08},
year = 2008
}