%0 Journal Article %1 journals/tvlsi/ChatterjeeRYM11 %A Chatterjee, Subho %A Rasquinha, Mitchelle %A Yalamanchili, Sudhakar %A Mukhopadhyay, Saibal %D 2011 %J IEEE Trans. Very Large Scale Integr. Syst. %K dblp %N 5 %P 809-817 %T A Scalable Design Methodology for Energy Minimization of STTRAM: A Circuit and Architecture Perspective. %U http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi19.html#ChatterjeeRYM11 %V 19

@article{journals/tvlsi/ChatterjeeRYM11, added-at = {2020-03-11T00:00:00.000+0100}, author = {Chatterjee, Subho and Rasquinha, Mitchelle and Yalamanchili, Sudhakar and Mukhopadhyay, Saibal}, biburl = {https://www.bibsonomy.org/bibtex/2b2380387e7f0316d6823bc530dfc890d/dblp}, ee = {https://doi.org/10.1109/TVLSI.2010.2041476}, interhash = {3d995a1744a97cb3947c56ff5213585a}, intrahash = {b2380387e7f0316d6823bc530dfc890d}, journal = {IEEE Trans. Very Large Scale Integr. Syst.}, keywords = {dblp}, number = 5, pages = {809-817}, timestamp = {2020-03-12T11:42:01.000+0100}, title = {A Scalable Design Methodology for Energy Minimization of STTRAM: A Circuit and Architecture Perspective.}, url = {http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi19.html#ChatterjeeRYM11}, volume = 19, year = 2011 }