%0 Conference Paper %1 conf/glvlsi/PomeranzR01 %A Pomeranz, Irith %A Reddy, Sudhakar M. %B ACM Great Lakes Symposium on VLSI %D 2001 %E Roy, Kaushik %E Kang, Sung-Mo %E Koh, Cheng-Kok %I ACM %K dblp %P 13-18 %T ITEM: an iterative improvement test generation procedure for synchronous sequential circuits. %U http://dblp.uni-trier.de/db/conf/glvlsi/glvlsi2001.html#PomeranzR01 %@ 1-58113-351-0

@inproceedings{conf/glvlsi/PomeranzR01, added-at = {2018-11-06T00:00:00.000+0100}, author = {Pomeranz, Irith and Reddy, Sudhakar M.}, biburl = {https://www.bibsonomy.org/bibtex/20bd7170b8b4220fb3efc5410dffd0f75/dblp}, booktitle = {ACM Great Lakes Symposium on VLSI}, crossref = {conf/glvlsi/2001}, editor = {Roy, Kaushik and Kang, Sung-Mo and Koh, Cheng-Kok}, ee = {https://doi.org/10.1145/368122.368147}, interhash = {41895a0745604138d5bdbb4bc24fb47c}, intrahash = {0bd7170b8b4220fb3efc5410dffd0f75}, isbn = {1-58113-351-0}, keywords = {dblp}, pages = {13-18}, publisher = {ACM}, timestamp = {2018-11-07T14:25:26.000+0100}, title = {ITEM: an iterative improvement test generation procedure for synchronous sequential circuits.}, url = {http://dblp.uni-trier.de/db/conf/glvlsi/glvlsi2001.html#PomeranzR01}, year = 2001 }