%0 Journal Article %1 journals/jcsc/WanZLDZ15 %A Wan, Meilin %A Zhang, Zhenzhen %A Liao, Wang %A Dai, Kui %A Zou, Xuecheng %D 2015 %J Journal of Circuits, Systems, and Computers %K dblp %N 7 %P 1550109:1-1550109:23 %T A 2/3 Dual-Modulus Prescaler Using Complementary Clocking NMOS-Like Blocks. %U http://dblp.uni-trier.de/db/journals/jcsc/jcsc24.html#WanZLDZ15 %V 24

@article{journals/jcsc/WanZLDZ15, added-at = {2019-12-18T00:00:00.000+0100}, author = {Wan, Meilin and Zhang, Zhenzhen and Liao, Wang and Dai, Kui and Zou, Xuecheng}, biburl = {https://www.bibsonomy.org/bibtex/2eccacde0c70910fe65b8a89bc65f846a/dblp}, ee = {https://doi.org/10.1142/S0218126615501091}, interhash = {42c45f36fdcf910ddb4688a983941cff}, intrahash = {eccacde0c70910fe65b8a89bc65f846a}, journal = {Journal of Circuits, Systems, and Computers}, keywords = {dblp}, number = 7, pages = {1550109:1-1550109:23}, timestamp = {2019-12-19T11:43:59.000+0100}, title = {A 2/3 Dual-Modulus Prescaler Using Complementary Clocking NMOS-Like Blocks.}, url = {http://dblp.uni-trier.de/db/journals/jcsc/jcsc24.html#WanZLDZ15}, volume = 24, year = 2015 }