%0 Journal Article %1 journals/vlsisp/AndreopoulosSLMC03 %A Andreopoulos, Yiannis %A Schelkens, Peter %A Lafruit, Gauthier %A Masselos, Kostas %A Cornelis, Jan %D 2003 %J VLSI Signal Processing %K dblp %N 3 %P 209-226 %T High-Level Cache Modeling for 2-D Discrete Wavelet Transform Implementations. %U http://dblp.uni-trier.de/db/journals/vlsisp/vlsisp34.html#AndreopoulosSLMC03 %V 34

@article{journals/vlsisp/AndreopoulosSLMC03, added-at = {2019-10-19T00:00:00.000+0200}, author = {Andreopoulos, Yiannis and Schelkens, Peter and Lafruit, Gauthier and Masselos, Kostas and Cornelis, Jan}, biburl = {https://www.bibsonomy.org/bibtex/25036604a2152d4b998613daa2888c176/dblp}, ee = {https://doi.org/10.1023/A:1023244201750}, interhash = {453182d1387fead8c9218595b2e9f458}, intrahash = {5036604a2152d4b998613daa2888c176}, journal = {VLSI Signal Processing}, keywords = {dblp}, number = 3, pages = {209-226}, timestamp = {2019-10-22T12:58:15.000+0200}, title = {High-Level Cache Modeling for 2-D Discrete Wavelet Transform Implementations.}, url = {http://dblp.uni-trier.de/db/journals/vlsisp/vlsisp34.html#AndreopoulosSLMC03}, volume = 34, year = 2003 }