%0 Journal Article %1 journals/vlsisp/ChenCCHC08a %A Chen, Yi-Hau %A Chen, Tung-Chien %A Chien, Shao-Yi %A Huang, Yu-Wen %A Chen, Liang-Gee %D 2008 %J J. Signal Process. Syst. %K dblp %N 3 %P 335-347 %T VLSI Architecture Design of Fractional Motion Estimation for H.264/AVC. %U http://dblp.uni-trier.de/db/journals/vlsisp/vlsisp53.html#ChenCCHC08a %V 53

@article{journals/vlsisp/ChenCCHC08a, added-at = {2024-02-05T00:00:00.000+0100}, author = {Chen, Yi-Hau and Chen, Tung-Chien and Chien, Shao-Yi and Huang, Yu-Wen and Chen, Liang-Gee}, biburl = {https://www.bibsonomy.org/bibtex/2755319e6a31e5ac32d99798820ce8e81/dblp}, ee = {https://doi.org/10.1007/s11265-008-0213-7}, interhash = {464504c1183caa76fe141a9cf1223a88}, intrahash = {755319e6a31e5ac32d99798820ce8e81}, journal = {J. Signal Process. Syst.}, keywords = {dblp}, number = 3, pages = {335-347}, timestamp = {2024-04-09T03:12:32.000+0200}, title = {VLSI Architecture Design of Fractional Motion Estimation for H.264/AVC.}, url = {http://dblp.uni-trier.de/db/journals/vlsisp/vlsisp53.html#ChenCCHC08a}, volume = 53, year = 2008 }