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%0 Conference Paper
%1 conf/ieeehpcs/YebenesMEGQ16
%A Yébenes, Pedro
%A Mathey, German Maglione
%A Escudero-Sahuquillo, Jesús
%A García, Pedro Javier
%A Quiles, Francisco J.
%B HPCS
%D 2016
%I IEEE
%K dblp
%P 380-386
%T Modeling a switch architecture with virtual output queues and virtual channels in HPC-systems simulators.
%U http://dblp.uni-trier.de/db/conf/ieeehpcs/ieeehpcs2016.html#YebenesMEGQ16
%@ 978-1-5090-2088-1
@inproceedings{conf/ieeehpcs/YebenesMEGQ16,
added-at = {2017-06-27T00:00:00.000+0200},
author = {Yébenes, Pedro and Mathey, German Maglione and Escudero-Sahuquillo, Jesús and García, Pedro Javier and Quiles, Francisco J.},
biburl = {https://www.bibsonomy.org/bibtex/22477f2f9685e7f19366da87b24015201/dblp},
booktitle = {HPCS},
crossref = {conf/ieeehpcs/2016},
ee = {https://doi.org/10.1109/HPCSim.2016.7568360},
interhash = {4ebb0ec1d17bd7178b12cdd070359934},
intrahash = {2477f2f9685e7f19366da87b24015201},
isbn = {978-1-5090-2088-1},
keywords = {dblp},
pages = {380-386},
publisher = {IEEE},
timestamp = {2017-06-28T11:40:36.000+0200},
title = {Modeling a switch architecture with virtual output queues and virtual channels in HPC-systems simulators.},
url = {http://dblp.uni-trier.de/db/conf/ieeehpcs/ieeehpcs2016.html#YebenesMEGQ16},
year = 2016
}