%0 Journal Article %1 journals/jssc/NagarajFALR97 %A Nagaraj, Krishnaswamy %A Fetterman, H. Scott %A Anidjar, Joseph %A Lewis, Stephen H. %A Renninger, Robert G. %D 1997 %J IEEE J. Solid State Circuits %K dblp %N 3 %P 312-320 %T A 250-mW, 8-b, 52-Msamples/s parallel-pipelined A/D converter with reduced number of amplifiers. %U http://dblp.uni-trier.de/db/journals/jssc/jssc32.html#NagarajFALR97 %V 32

@article{journals/jssc/NagarajFALR97, added-at = {2022-07-07T00:00:00.000+0200}, author = {Nagaraj, Krishnaswamy and Fetterman, H. Scott and Anidjar, Joseph and Lewis, Stephen H. and Renninger, Robert G.}, biburl = {https://www.bibsonomy.org/bibtex/25a7e3a39eb208c7a418b180e931e37fb/dblp}, ee = {https://doi.org/10.1109/4.557628}, interhash = {57536943a56f00876c2be4f95b03eaac}, intrahash = {5a7e3a39eb208c7a418b180e931e37fb}, journal = {IEEE J. Solid State Circuits}, keywords = {dblp}, number = 3, pages = {312-320}, timestamp = {2024-04-08T10:43:31.000+0200}, title = {A 250-mW, 8-b, 52-Msamples/s parallel-pipelined A/D converter with reduced number of amplifiers.}, url = {http://dblp.uni-trier.de/db/journals/jssc/jssc32.html#NagarajFALR97}, volume = 32, year = 1997 }