Inproceedings,

Error control integration scheme for reliable NoC

, , , and .
Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on, page 3893-3896. (2010)
DOI: 10.1109/ISCAS.2010.5537694

Abstract

To improve noise tolerance of link transmission and router buffers, we propose an error control scheme that integrates a powerful link error recovery method, an efficient buffer error correction coding, and an algorithm to further manage the loss of header and tail flits in a packet. With this method, header and tail flits can be effectively protected, reducing network saturation. Simulation results show the proposed scheme achieves up to a 9x improvement in operation time before saturation and 26% higher throughput than other error control methods. Simulations performed on a parallel FFT application mapped on a 4×4 mesh NoC demonstrate that the proposed error control scheme reduces the total computation time over a previous method in the high noise region.

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