%0 Journal Article %1 journals/integration/QinWMMH20 %A Qin, Maoyuan %A Wang, Xinmu %A Mao, Baolei %A Mu, Dejun %A Hu, Wei %D 2020 %J Integr. %K dblp %P 123-133 %T A formal model for proving hardware timing properties and identifying timing channels. %U http://dblp.uni-trier.de/db/journals/integration/integration72.html#QinWMMH20 %V 72

@article{journals/integration/QinWMMH20, added-at = {2020-03-24T00:00:00.000+0100}, author = {Qin, Maoyuan and Wang, Xinmu and Mao, Baolei and Mu, Dejun and Hu, Wei}, biburl = {https://www.bibsonomy.org/bibtex/208259e13cea864ebc45c3e8ec3e9f102/dblp}, ee = {https://doi.org/10.1016/j.vlsi.2020.02.001}, interhash = {5c5efbe68bd9ec6b3f29842ea14e6e79}, intrahash = {08259e13cea864ebc45c3e8ec3e9f102}, journal = {Integr.}, keywords = {dblp}, pages = {123-133}, timestamp = {2020-03-25T11:40:23.000+0100}, title = {A formal model for proving hardware timing properties and identifying timing channels.}, url = {http://dblp.uni-trier.de/db/journals/integration/integration72.html#QinWMMH20}, volume = 72, year = 2020 }