%0 Conference Paper %1 conf/ised/DrechslerW12 %A Drechsler, Rolf %A Wille, Robert %B ISED %D 2012 %I IEEE %K dblp %P 1-5 %T Synthesis of Reversible Circuits Using Decision Diagrams. %U http://dblp.uni-trier.de/db/conf/ised/ised2012.html#DrechslerW12 %@ 978-1-4673-4704-4

@inproceedings{conf/ised/DrechslerW12, added-at = {2019-06-02T00:00:00.000+0200}, author = {Drechsler, Rolf and Wille, Robert}, biburl = {https://www.bibsonomy.org/bibtex/28e17ec1991c85585cc71a93c9e73b08d/dblp}, booktitle = {ISED}, crossref = {conf/ised/2012}, ee = {https://www.wikidata.org/entity/Q59242504}, interhash = {6081ae734c295666ca361a9b0c698998}, intrahash = {8e17ec1991c85585cc71a93c9e73b08d}, isbn = {978-1-4673-4704-4}, keywords = {dblp}, pages = {1-5}, publisher = {IEEE}, timestamp = {2019-10-17T15:14:40.000+0200}, title = {Synthesis of Reversible Circuits Using Decision Diagrams.}, url = {http://dblp.uni-trier.de/db/conf/ised/ised2012.html#DrechslerW12}, year = 2012 }