%0 Journal Article %1 journals/tcasII/MohapatraVC21 %A Mohapatra, Sucheta %A Vendra, Satya K. %A Chrzanowska-Jeske, Malgorzata %D 2021 %J IEEE Trans. Circuits Syst. II Express Briefs %K dblp %N 1 %P 271-275 %T Fast Buffer Count Estimation in 3D IC Floorplanning. %U http://dblp.uni-trier.de/db/journals/tcasII/tcasII68.html#MohapatraVC21 %V 68

@article{journals/tcasII/MohapatraVC21, added-at = {2021-03-23T00:00:00.000+0100}, author = {Mohapatra, Sucheta and Vendra, Satya K. and Chrzanowska-Jeske, Malgorzata}, biburl = {https://www.bibsonomy.org/bibtex/2c3c9b5e492628352f3e307b523698712/dblp}, ee = {https://doi.org/10.1109/TCSII.2020.3007858}, interhash = {649894b349ce8b5f58e18538645d0723}, intrahash = {c3c9b5e492628352f3e307b523698712}, journal = {IEEE Trans. Circuits Syst. II Express Briefs}, keywords = {dblp}, number = 1, pages = {271-275}, timestamp = {2024-04-08T16:53:42.000+0200}, title = {Fast Buffer Count Estimation in 3D IC Floorplanning.}, url = {http://dblp.uni-trier.de/db/journals/tcasII/tcasII68.html#MohapatraVC21}, volume = 68, year = 2021 }