%0 Journal Article %1 journals/ojcands/GrossMA21 %A Gross, Warren J. %A Meyer, Brett H. %A Ardakani, Arash %D 2021 %J IEEE Open J. Circuits Syst. %K dblp %P 113-127 %T Hardware-Aware Design for Edge Intelligence. %U http://dblp.uni-trier.de/db/journals/ojcands/ojcands2.html#GrossMA21 %V 2

@article{journals/ojcands/GrossMA21, added-at = {2023-08-28T00:00:00.000+0200}, author = {Gross, Warren J. and Meyer, Brett H. and Ardakani, Arash}, biburl = {https://www.bibsonomy.org/bibtex/2a06d27149175e5b67da925798344edd2/dblp}, ee = {https://www.wikidata.org/entity/Q114985840}, interhash = {6a4f978199f4a3975672e13e4f78669d}, intrahash = {a06d27149175e5b67da925798344edd2}, journal = {IEEE Open J. Circuits Syst.}, keywords = {dblp}, pages = {113-127}, timestamp = {2024-04-08T21:16:28.000+0200}, title = {Hardware-Aware Design for Edge Intelligence.}, url = {http://dblp.uni-trier.de/db/journals/ojcands/ojcands2.html#GrossMA21}, volume = 2, year = 2021 }