%0 Conference Paper %1 conf/vlsic/MeterelliyozAAH14 %A Meterelliyoz, Mesut %A Al amoody, Fuad H. %A Arslan, Umut %A Hamzaoglu, Fatih %A Hood, Luke %A Lal, Manoj B. %A Miller, Jeffrey L. %A Ramasundar, Anand %A Soltman, Dan %A Wan, Ifar %A Wang, Yih %A Zhang, Kevin %B VLSIC %D 2014 %I IEEE %K dblp %P 1-2 %T 2nd generation embedded DRAM with 4X lower self refresh power in 22nm Tri-Gate CMOS technology. %U http://dblp.uni-trier.de/db/conf/vlsic/vlsic2014.html#MeterelliyozAAH14 %@ 978-1-4799-3327-3

@inproceedings{conf/vlsic/MeterelliyozAAH14, added-at = {2017-05-21T00:00:00.000+0200}, author = {Meterelliyoz, Mesut and Al amoody, Fuad H. and Arslan, Umut and Hamzaoglu, Fatih and Hood, Luke and Lal, Manoj B. and Miller, Jeffrey L. and Ramasundar, Anand and Soltman, Dan and Wan, Ifar and Wang, Yih and Zhang, Kevin}, biburl = {https://www.bibsonomy.org/bibtex/2e3e9efe4701874850d14df53f862ec5d/dblp}, booktitle = {VLSIC}, crossref = {conf/vlsic/2014}, ee = {https://doi.org/10.1109/VLSIC.2014.6858415}, interhash = {77601b4cfb1c98cace284166bab2f7c1}, intrahash = {e3e9efe4701874850d14df53f862ec5d}, isbn = {978-1-4799-3327-3}, keywords = {dblp}, pages = {1-2}, publisher = {IEEE}, timestamp = {2017-05-24T05:33:44.000+0200}, title = {2nd generation embedded DRAM with 4X lower self refresh power in 22nm Tri-Gate CMOS technology.}, url = {http://dblp.uni-trier.de/db/conf/vlsic/vlsic2014.html#MeterelliyozAAH14}, year = 2014 }