%0 Journal Article %1 journals/vlsisp/WangPHLLCWC05 %A Wang, Shih-Hao %A Peng, Wen-Hsiao %A He, Yuwen %A Lin, Guan-Yi %A Lin, Cheng-Yi %A Chang, Shih-Chien %A Wang, Chung-Neng %A Chiang, Tihao %D 2005 %J J. VLSI Signal Process. %K dblp %N 1 %P 93-110 %T A Software-Hardware Co-Implementation of MPEG-4 Advanced Video Coding (AVC) Decoder with Block Level Pipelining. %U http://dblp.uni-trier.de/db/journals/vlsisp/vlsisp41.html#WangPHLLCWC05 %V 41

@article{journals/vlsisp/WangPHLLCWC05, added-at = {2023-03-21T00:00:00.000+0100}, author = {Wang, Shih-Hao and Peng, Wen-Hsiao and He, Yuwen and Lin, Guan-Yi and Lin, Cheng-Yi and Chang, Shih-Chien and Wang, Chung-Neng and Chiang, Tihao}, biburl = {https://www.bibsonomy.org/bibtex/22ed790f5112010425032576ab44d4764/dblp}, ee = {https://doi.org/10.1007/s11265-005-6253-3}, interhash = {77adc64abb5361db0dae2ecc8a734ac9}, intrahash = {2ed790f5112010425032576ab44d4764}, journal = {J. VLSI Signal Process.}, keywords = {dblp}, number = 1, pages = {93-110}, timestamp = {2024-04-09T03:12:05.000+0200}, title = {A Software-Hardware Co-Implementation of MPEG-4 Advanced Video Coding (AVC) Decoder with Block Level Pipelining.}, url = {http://dblp.uni-trier.de/db/journals/vlsisp/vlsisp41.html#WangPHLLCWC05}, volume = 41, year = 2005 }