%0 Conference Paper %1 conf/vlsid/AdigaASSFS10 %A Adiga, Raghavendra %A Arpit, Gandhi %A Singh, Virendra %A Saluja, Kewal K. %A Fujiwara, Hideo %A Singh, Adit D. %B VLSI Design %D 2010 %I IEEE Computer Society %K dblp %P 393-398 %T On Minimization of Test Application Time for RAS. %U http://dblp.uni-trier.de/db/conf/vlsid/vlsid2010.html#AdigaASSFS10 %@ 978-0-7695-3928-7

@inproceedings{conf/vlsid/AdigaASSFS10, added-at = {2023-03-24T00:00:00.000+0100}, author = {Adiga, Raghavendra and Arpit, Gandhi and Singh, Virendra and Saluja, Kewal K. and Fujiwara, Hideo and Singh, Adit D.}, biburl = {https://www.bibsonomy.org/bibtex/2b0bd5e9eb9c6a895d879af99d2805c43/dblp}, booktitle = {VLSI Design}, crossref = {conf/vlsid/2010}, ee = {https://doi.ieeecomputersociety.org/10.1109/VLSI.Design.2010.61}, interhash = {8c0bc8434d3a73451befe536a3521439}, intrahash = {b0bd5e9eb9c6a895d879af99d2805c43}, isbn = {978-0-7695-3928-7}, keywords = {dblp}, pages = {393-398}, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T04:17:37.000+0200}, title = {On Minimization of Test Application Time for RAS.}, url = {http://dblp.uni-trier.de/db/conf/vlsid/vlsid2010.html#AdigaASSFS10}, year = 2010 }