%0 Conference Paper %1 conf/vlsi/CimatoCDE17 %A Cimato, Stelvio %A Ciriani, Valentina %A Damiani, Ernesto %A Ehsanpour, Maryam %B VLSI-SoC %D 2017 %I IEEE %K dblp %P 1-5 %T A multiple valued logic approach for the synthesis of garbled circuits. %U http://dblp.uni-trier.de/db/conf/vlsi/vlsisoc2017.html#CimatoCDE17 %@ 978-1-5386-2880-5

@inproceedings{conf/vlsi/CimatoCDE17, added-at = {2020-06-15T00:00:00.000+0200}, author = {Cimato, Stelvio and Ciriani, Valentina and Damiani, Ernesto and Ehsanpour, Maryam}, biburl = {https://www.bibsonomy.org/bibtex/2251a82b8b1dd121d06b9751be353ef2b/dblp}, booktitle = {VLSI-SoC}, crossref = {conf/vlsi/2017soc}, ee = {https://doi.org/10.1109/VLSI-SoC.2017.8203495}, interhash = {8f344e02b65ff9a67203be15d1eacdab}, intrahash = {251a82b8b1dd121d06b9751be353ef2b}, isbn = {978-1-5386-2880-5}, keywords = {dblp}, pages = {1-5}, publisher = {IEEE}, timestamp = {2020-06-16T13:10:04.000+0200}, title = {A multiple valued logic approach for the synthesis of garbled circuits.}, url = {http://dblp.uni-trier.de/db/conf/vlsi/vlsisoc2017.html#CimatoCDE17}, year = 2017 }