%0 Journal Article %1 journals/todaes/CongH00 %A Cong, Jason %A Hwang, Yean-Yow %D 2000 %J ACM Trans. Design Autom. Electr. Syst. %K dblp %N 2 %P 193-225 %T Structural gate decomposition for depth-optimal technology mapping in LUT-based FPGA designs. %U http://dblp.uni-trier.de/db/journals/todaes/todaes5.html#CongH00 %V 5

@article{journals/todaes/CongH00, added-at = {2018-11-06T00:00:00.000+0100}, author = {Cong, Jason and Hwang, Yean-Yow}, biburl = {https://www.bibsonomy.org/bibtex/2f97486270d2e809c029e1269109b2385/dblp}, ee = {https://doi.org/10.1145/335043.335045}, interhash = {9370507be2785c0d13d315f0fffe2d07}, intrahash = {f97486270d2e809c029e1269109b2385}, journal = {ACM Trans. Design Autom. Electr. Syst.}, keywords = {dblp}, number = 2, pages = {193-225}, timestamp = {2018-11-07T12:24:07.000+0100}, title = {Structural gate decomposition for depth-optimal technology mapping in LUT-based FPGA designs.}, url = {http://dblp.uni-trier.de/db/journals/todaes/todaes5.html#CongH00}, volume = 5, year = 2000 }