%0 Conference Paper %1 conf/isvlsi/OreifejAE06 %A Oreifej, Rashad S. %A Alsharqawi, Abdelhalim %A Ejnioui, Abdel %B ISVLSI %D 2006 %I IEEE Computer Society %K dblp %P 71-76 %T Synthesis of Pipelined SRSL Circuits. %U http://dblp.uni-trier.de/db/conf/isvlsi/isvlsi2006.html#OreifejAE06 %@ 0-7695-2533-4

@inproceedings{conf/isvlsi/OreifejAE06, added-at = {2023-03-24T00:00:00.000+0100}, author = {Oreifej, Rashad S. and Alsharqawi, Abdelhalim and Ejnioui, Abdel}, biburl = {https://www.bibsonomy.org/bibtex/263ad225547229c5665d7256cb5f570cb/dblp}, booktitle = {ISVLSI}, crossref = {conf/isvlsi/2006}, ee = {https://doi.ieeecomputersociety.org/10.1109/ISVLSI.2006.86}, interhash = {9455d19b84743c32dcbfab58ee60a4c3}, intrahash = {63ad225547229c5665d7256cb5f570cb}, isbn = {0-7695-2533-4}, keywords = {dblp}, pages = {71-76}, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T11:06:14.000+0200}, title = {Synthesis of Pipelined SRSL Circuits.}, url = {http://dblp.uni-trier.de/db/conf/isvlsi/isvlsi2006.html#OreifejAE06}, year = 2006 }