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15.5 A 28nm 64Kb 6T SRAM Computing-in-Memory Macro with 8b MAC Operation for AI Edge Chips.
X. Si, Y. Tu, W. Huang, J. Su, P. Lu, J. Wang, T. Liu, S. Wu, R. Liu, Y. Chou, Z. Zhang, S. Sie, W. Wei, Y. Lo, T. Wen, T. Hsu, Y. Chen, W. Shih, C. Lo, R. Liu, C. Hsieh, K. Tang, N. Lien, W. Shih, Y. He, Q. Li, und M. Chang.ISSCC, Seite 246-248. IEEE, (2020)
Metadaten
- BibTeX-Schlüssel
- conf/isscc/SiTHSLWLWLCZSWL20
- Eintragstyp
- inproceedings
- Buchtitel
- ISSCC
- Jahr
- 2020
- Seiten
- 246-248
- Verlag
- IEEE
- BibTeX-Querverweis
- conf/isscc/2020
- ee
- https://doi.org/10.1109/ISSCC19947.2020.9062995
- isbn
- 978-1-7281-3205-1
- URL
- http://dblp.uni-trier.de/db/conf/isscc/isscc2020.html#SiTHSLWLWLCZSWL20
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%1 conf/isscc/SiTHSLWLWLCZSWL20
%A Si, Xin
%A Tu, Yung-Ning
%A Huang, Wei-Hsing
%A Su, Jian-Wei
%A Lu, Pei-Jung
%A Wang, Jing-Hong
%A Liu, Ta-Wei
%A Wu, Ssu-Yen
%A Liu, Ruhui
%A Chou, Yen-Chi
%A Zhang, Zhixiao
%A Sie, Syuan-Hao
%A Wei, Wei-Chen
%A Lo, Yun-Chen
%A Wen, Tai-Hsing
%A Hsu, Tzu-Hsiang
%A Chen, Yen-Kai
%A Shih, William
%A Lo, Chung-Chuan
%A Liu, Ren-Shuo
%A Hsieh, Chih-Cheng
%A Tang, Kea-Tiong
%A Lien, Nan-Chun
%A Shih, Wei-Chiang
%A He, Yajuan
%A Li, Qiang
%A Chang, Meng-Fan
%B ISSCC
%D 2020
%I IEEE
%K dblp
%P 246-248
%T 15.5 A 28nm 64Kb 6T SRAM Computing-in-Memory Macro with 8b MAC Operation for AI Edge Chips.
%U http://dblp.uni-trier.de/db/conf/isscc/isscc2020.html#SiTHSLWLWLCZSWL20
%@ 978-1-7281-3205-1
@inproceedings{conf/isscc/SiTHSLWLWLCZSWL20,
added-at = {2024-05-07T00:00:00.000+0200},
author = {Si, Xin and Tu, Yung-Ning and Huang, Wei-Hsing and Su, Jian-Wei and Lu, Pei-Jung and Wang, Jing-Hong and Liu, Ta-Wei and Wu, Ssu-Yen and Liu, Ruhui and Chou, Yen-Chi and Zhang, Zhixiao and Sie, Syuan-Hao and Wei, Wei-Chen and Lo, Yun-Chen and Wen, Tai-Hsing and Hsu, Tzu-Hsiang and Chen, Yen-Kai and Shih, William and Lo, Chung-Chuan and Liu, Ren-Shuo and Hsieh, Chih-Cheng and Tang, Kea-Tiong and Lien, Nan-Chun and Shih, Wei-Chiang and He, Yajuan and Li, Qiang and Chang, Meng-Fan},
biburl = {https://www.bibsonomy.org/bibtex/2e5020b966d6492fd2593b7635ad9ffea/dblp},
booktitle = {ISSCC},
crossref = {conf/isscc/2020},
ee = {https://doi.org/10.1109/ISSCC19947.2020.9062995},
interhash = {a807f7a0f0d17ae9d35a16580dc5c16f},
intrahash = {e5020b966d6492fd2593b7635ad9ffea},
isbn = {978-1-7281-3205-1},
keywords = {dblp},
pages = {246-248},
publisher = {IEEE},
timestamp = {2024-05-13T09:02:23.000+0200},
title = {15.5 A 28nm 64Kb 6T SRAM Computing-in-Memory Macro with 8b MAC Operation for AI Edge Chips.},
url = {http://dblp.uni-trier.de/db/conf/isscc/isscc2020.html#SiTHSLWLWLCZSWL20},
year = 2020
}