%0 Conference Paper %1 conf/icecsys/NicolleGFTJ05 %A Nicolle, Benjamin %A Geynet, Lionel %A de Foucauld, Emeric %A Tatinian, William %A Jacquemod, Gilles %B ICECS %D 2005 %I IEEE %K dblp %P 1-4 %T VHDL-AMS modeling of a multi-standard phase locked loop. %U http://dblp.uni-trier.de/db/conf/icecsys/icecsys2005.html#NicolleGFTJ05 %@ 978-9972-61-100-1

@inproceedings{conf/icecsys/NicolleGFTJ05, added-at = {2017-05-23T00:00:00.000+0200}, author = {Nicolle, Benjamin and Geynet, Lionel and de Foucauld, Emeric and Tatinian, William and Jacquemod, Gilles}, biburl = {https://www.bibsonomy.org/bibtex/29b3a44e816b24cba50b8c913b71c4500/dblp}, booktitle = {ICECS}, crossref = {conf/icecsys/2005}, ee = {https://doi.org/10.1109/ICECS.2005.4633374}, interhash = {acef1e9c53ec9edc4441373447b64383}, intrahash = {9b3a44e816b24cba50b8c913b71c4500}, isbn = {978-9972-61-100-1}, keywords = {dblp}, pages = {1-4}, publisher = {IEEE}, timestamp = {2019-10-17T19:50:35.000+0200}, title = {VHDL-AMS modeling of a multi-standard phase locked loop.}, url = {http://dblp.uni-trier.de/db/conf/icecsys/icecsys2005.html#NicolleGFTJ05}, year = 2005 }