%0 Journal Article %1 journals/ieicet/HigamiSTKT08 %A Higami, Yoshinobu %A Saluja, Kewal K. %A Takahashi, Hiroshi %A ya Kobayashi, Shin %A Takamatsu, Yuzo %D 2008 %J IEICE Trans. Inf. Syst. %K dblp %N 3 %P 690-699 %T Fault Simulation and Test Generation for Transistor Shorts Using Stuck-at Test Tools. %U http://dblp.uni-trier.de/db/journals/ieicet/ieicet91d.html#HigamiSTKT08 %V 91-D

@article{journals/ieicet/HigamiSTKT08, added-at = {2020-04-11T00:00:00.000+0200}, author = {Higami, Yoshinobu and Saluja, Kewal K. and Takahashi, Hiroshi and ya Kobayashi, Shin and Takamatsu, Yuzo}, biburl = {https://www.bibsonomy.org/bibtex/210738f2e988cd0da84caf429c9a07ed8/dblp}, ee = {https://doi.org/10.1093/ietisy/e91-d.3.690}, interhash = {ae15569a0f4c6f67fbdcaa2841092cfe}, intrahash = {10738f2e988cd0da84caf429c9a07ed8}, journal = {IEICE Trans. Inf. Syst.}, keywords = {dblp}, number = 3, pages = {690-699}, timestamp = {2020-04-14T11:58:13.000+0200}, title = {Fault Simulation and Test Generation for Transistor Shorts Using Stuck-at Test Tools.}, url = {http://dblp.uni-trier.de/db/journals/ieicet/ieicet91d.html#HigamiSTKT08}, volume = {91-D}, year = 2008 }