%0 Journal Article %1 journals/vlsisp/WangHSL12 %A Wang, Chua-Chin %A Hsu, Chia-Hao %A Sung, Gang-Neng %A Lu, Yu-Cheng %D 2012 %J J. Signal Process. Syst. %K dblp %N 2 %P 87-92 %T A Signed Array Multiplier with Bypassing Logic. %U http://dblp.uni-trier.de/db/journals/vlsisp/vlsisp66.html#WangHSL12 %V 66

@article{journals/vlsisp/WangHSL12, added-at = {2020-03-12T00:00:00.000+0100}, author = {Wang, Chua-Chin and Hsu, Chia-Hao and Sung, Gang-Neng and Lu, Yu-Cheng}, biburl = {https://www.bibsonomy.org/bibtex/20e86912498aca318930281c2abd3b772/dblp}, ee = {https://doi.org/10.1007/s11265-010-0558-6}, interhash = {b96b5e108767da54b512cecaa5343bce}, intrahash = {0e86912498aca318930281c2abd3b772}, journal = {J. Signal Process. Syst.}, keywords = {dblp}, number = 2, pages = {87-92}, timestamp = {2020-03-13T12:00:45.000+0100}, title = {A Signed Array Multiplier with Bypassing Logic.}, url = {http://dblp.uni-trier.de/db/journals/vlsisp/vlsisp66.html#WangHSL12}, volume = 66, year = 2012 }