%0 Journal Article %1 journals/jssc/ChangHSBCCCGLLR07 %A Chang, Jonathan %A Huang, Ming %A Shoemaker, Jonathan %A Benoit, John %A Chen, Szu-Liang %A Chen, Wei %A Chiu, Siufu %A Ganesan, Raghuraman %A Leong, Gloria %A Lukka, Venkata %A Rusu, Stefan %A Srivastava, Durgesh %D 2007 %J IEEE J. Solid State Circuits %K dblp %N 4 %P 846-852 %T The 65-nm 16-MB Shared On-Die L3 Cache for the Dual-Core Intel Xeon Processor 7100 Series. %U http://dblp.uni-trier.de/db/journals/jssc/jssc42.html#ChangHSBCCCGLLR07 %V 42

@article{journals/jssc/ChangHSBCCCGLLR07, added-at = {2023-02-10T00:00:00.000+0100}, author = {Chang, Jonathan and Huang, Ming and Shoemaker, Jonathan and Benoit, John and Chen, Szu-Liang and Chen, Wei and Chiu, Siufu and Ganesan, Raghuraman and Leong, Gloria and Lukka, Venkata and Rusu, Stefan and Srivastava, Durgesh}, biburl = {https://www.bibsonomy.org/bibtex/208bf27d5a14888b0fe16abdb41aad59b/dblp}, ee = {https://doi.org/10.1109/JSSC.2007.892185}, interhash = {bb8d85337e90fc897bff15a2b093e030}, intrahash = {08bf27d5a14888b0fe16abdb41aad59b}, journal = {IEEE J. Solid State Circuits}, keywords = {dblp}, number = 4, pages = {846-852}, timestamp = {2024-04-08T10:43:40.000+0200}, title = {The 65-nm 16-MB Shared On-Die L3 Cache for the Dual-Core Intel Xeon Processor 7100 Series.}, url = {http://dblp.uni-trier.de/db/journals/jssc/jssc42.html#ChangHSBCCCGLLR07}, volume = 42, year = 2007 }