Artikel,
A 8-b-Precision 6T SRAM Computing-in-Memory Macro Using Segmented-Bitline Charge-Sharing Scheme for AI Edge Chips.
J. Su, Y. Chou, R. Liu, T. Liu, P. Lu, P. Wu, Y. Chung, L. Hong, J. Ren, T. Pan, C. Jhang, W. Huang, C. Chien, P. Mei, S. Li, S. Sheu, S. Chang, W. Lo, C. Wu, X. Si, C. Lo, R. Liu, C. Hsieh, K. Tang, und M. Chang.IEEE J. Solid State Circuits, 58 (3): 877-892 (März 2023)
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- BibTeX-Schlüssel
- journals/jssc/SuCLLLWCHRPJHCMLSCLWSLLHTC23
- Eintragstyp
- article
- Jahr
- 2023
- Monat
- March
- Zeitschrift
- IEEE J. Solid State Circuits
- Nummer
- 3
- Seiten
- 877-892
- Band
- 58
- ee
- https://www.wikidata.org/entity/Q117044471
- URL
- http://dblp.uni-trier.de/db/journals/jssc/jssc58.html#SuCLLLWCHRPJHCMLSCLWSLLHTC23
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%1 journals/jssc/SuCLLLWCHRPJHCMLSCLWSLLHTC23
%A Su, Jian-Wei
%A Chou, Yen-Chi
%A Liu, Ruhui
%A Liu, Ta-Wei
%A Lu, Pei-Jung
%A Wu, Ping-Chun
%A Chung, Yen-Lin
%A Hong, Li-Yang
%A Ren, Jin-Sheng
%A Pan, Tianlong
%A Jhang, Chuan-Jia
%A Huang, Wei-Hsing
%A Chien, Chih-Han
%A Mei, Peng-I
%A Li, Sih-Han
%A Sheu, Shyh-Shyuan
%A Chang, Shih-Chieh
%A Lo, Wei-Chung
%A Wu, Chih-I
%A Si, Xin
%A Lo, Chung-Chuan
%A Liu, Ren-Shuo
%A Hsieh, Chih-Cheng
%A Tang, Kea-Tiong
%A Chang, Meng-Fan
%D 2023
%J IEEE J. Solid State Circuits
%K dblp
%N 3
%P 877-892
%T A 8-b-Precision 6T SRAM Computing-in-Memory Macro Using Segmented-Bitline Charge-Sharing Scheme for AI Edge Chips.
%U http://dblp.uni-trier.de/db/journals/jssc/jssc58.html#SuCLLLWCHRPJHCMLSCLWSLLHTC23
%V 58
@article{journals/jssc/SuCLLLWCHRPJHCMLSCLWSLLHTC23,
added-at = {2023-08-28T00:00:00.000+0200},
author = {Su, Jian-Wei and Chou, Yen-Chi and Liu, Ruhui and Liu, Ta-Wei and Lu, Pei-Jung and Wu, Ping-Chun and Chung, Yen-Lin and Hong, Li-Yang and Ren, Jin-Sheng and Pan, Tianlong and Jhang, Chuan-Jia and Huang, Wei-Hsing and Chien, Chih-Han and Mei, Peng-I and Li, Sih-Han and Sheu, Shyh-Shyuan and Chang, Shih-Chieh and Lo, Wei-Chung and Wu, Chih-I and Si, Xin and Lo, Chung-Chuan and Liu, Ren-Shuo and Hsieh, Chih-Cheng and Tang, Kea-Tiong and Chang, Meng-Fan},
biburl = {https://www.bibsonomy.org/bibtex/2e28e7cfe40f4f89798bf1b1379e44e86/dblp},
ee = {https://www.wikidata.org/entity/Q117044471},
interhash = {bec3f0d9ed193eba051a8d5f97e31ab9},
intrahash = {e28e7cfe40f4f89798bf1b1379e44e86},
journal = {IEEE J. Solid State Circuits},
keywords = {dblp},
month = {March},
number = 3,
pages = {877-892},
timestamp = {2024-04-08T10:43:23.000+0200},
title = {A 8-b-Precision 6T SRAM Computing-in-Memory Macro Using Segmented-Bitline Charge-Sharing Scheme for AI Edge Chips.},
url = {http://dblp.uni-trier.de/db/journals/jssc/jssc58.html#SuCLLLWCHRPJHCMLSCLWSLLHTC23},
volume = 58,
year = 2023
}