%0 Journal Article %1 journals/tcad/LeeTW96 %A Lee, Jin-Fuw %A Tang, Donald T. %A Wong, Chak-Kuen %D 1996 %J IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. %K dblp %N 5 %P 535-543 %T A timing analysis algorithm for circuits with level-sensitive latches. %U http://dblp.uni-trier.de/db/journals/tcad/tcad15.html#LeeTW96 %V 15

@article{journals/tcad/LeeTW96, added-at = {2021-09-06T00:00:00.000+0200}, author = {Lee, Jin-Fuw and Tang, Donald T. and Wong, Chak-Kuen}, biburl = {https://www.bibsonomy.org/bibtex/2c3cfd06c085b1b5c91a546bd8d4ad02a/dblp}, ee = {https://doi.org/10.1109/43.506140}, interhash = {c343d0df17898d51f03fbf2a533436d7}, intrahash = {c3cfd06c085b1b5c91a546bd8d4ad02a}, journal = {IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.}, keywords = {dblp}, number = 5, pages = {535-543}, timestamp = {2024-04-08T19:45:35.000+0200}, title = {A timing analysis algorithm for circuits with level-sensitive latches.}, url = {http://dblp.uni-trier.de/db/journals/tcad/tcad15.html#LeeTW96}, volume = 15, year = 1996 }