%0 Conference Paper %1 conf/isocc/LeeKS17 %A Lee, Yongho %A Kim, Seungsoo %A Shin, Hyunchol %B ISOCC %D 2017 %I IEEE %K dblp %P 230-231 %T Design of a 1-V 3-mW 2.4-GHz fractional-N PLL synthesizer in 65nm CMOS. %U http://dblp.uni-trier.de/db/conf/isocc/isocc2017.html#LeeKS17 %@ 978-1-5386-2285-8

@inproceedings{conf/isocc/LeeKS17, added-at = {2018-06-15T00:00:00.000+0200}, author = {Lee, Yongho and Kim, Seungsoo and Shin, Hyunchol}, biburl = {https://www.bibsonomy.org/bibtex/262a48c12d66bbe916c66e8ed22b28924/dblp}, booktitle = {ISOCC}, crossref = {conf/isocc/2017}, ee = {https://doi.org/10.1109/ISOCC.2017.8368867}, interhash = {c395f946c7918de28be2c4193f352008}, intrahash = {62a48c12d66bbe916c66e8ed22b28924}, isbn = {978-1-5386-2285-8}, keywords = {dblp}, pages = {230-231}, publisher = {IEEE}, timestamp = {2019-02-28T11:42:14.000+0100}, title = {Design of a 1-V 3-mW 2.4-GHz fractional-N PLL synthesizer in 65nm CMOS.}, url = {http://dblp.uni-trier.de/db/conf/isocc/isocc2017.html#LeeKS17}, year = 2017 }