%0 Conference Paper %1 conf/dac/AlawiehWL17 %A Alawieh, Mohamad Baker %A Wang, Fa %A Li, Xin %B DAC %D 2017 %I ACM %K dblp %P 9:1-9:6 %T Efficient Hierarchical Performance Modeling for Integrated Circuits via Bayesian Co-Learning. %U http://dblp.uni-trier.de/db/conf/dac/dac2017.html#AlawiehWL17 %@ 978-1-4503-4927-7

@inproceedings{conf/dac/AlawiehWL17, added-at = {2019-10-19T00:00:00.000+0200}, author = {Alawieh, Mohamad Baker and Wang, Fa and Li, Xin}, biburl = {https://www.bibsonomy.org/bibtex/24201431fa06df5634a57c3665a3ab54a/dblp}, booktitle = {DAC}, crossref = {conf/dac/2017}, ee = {https://doi.org/10.1145/3061639.3062235}, interhash = {c56ac23d8fb4b787ca95a180b28214d7}, intrahash = {4201431fa06df5634a57c3665a3ab54a}, isbn = {978-1-4503-4927-7}, keywords = {dblp}, pages = {9:1-9:6}, publisher = {ACM}, timestamp = {2019-10-22T14:40:57.000+0200}, title = {Efficient Hierarchical Performance Modeling for Integrated Circuits via Bayesian Co-Learning.}, url = {http://dblp.uni-trier.de/db/conf/dac/dac2017.html#AlawiehWL17}, year = 2017 }