%0 Conference Paper %1 conf/vlsic/ZhangCHT16 %A Zhang, Yi %A Chen, Chia-Hung %A He, Tao %A Temes, Gabor C. %B VLSI Circuits %D 2016 %I IEEE %K dblp %P 1-2 %T A 35µW 96.8dB SNDR 1 kHz BW multi-step incremental ADC using multi-slope extended counting with a single integrator. %U http://dblp.uni-trier.de/db/conf/vlsic/vlsic2016.html#ZhangCHT16 %@ 978-1-5090-0635-9

@inproceedings{conf/vlsic/ZhangCHT16, added-at = {2018-01-10T00:00:00.000+0100}, author = {Zhang, Yi and Chen, Chia-Hung and He, Tao and Temes, Gabor C.}, biburl = {https://www.bibsonomy.org/bibtex/2eadc55f5a9c5e4b7d27f54f6747fd6af/dblp}, booktitle = {VLSI Circuits}, crossref = {conf/vlsic/2016}, ee = {https://doi.org/10.1109/VLSIC.2016.7573464}, interhash = {c889210abaca12716efa0a4bb8f83bab}, intrahash = {eadc55f5a9c5e4b7d27f54f6747fd6af}, isbn = {978-1-5090-0635-9}, keywords = {dblp}, pages = {1-2}, publisher = {IEEE}, timestamp = {2018-01-11T11:37:19.000+0100}, title = {A 35µW 96.8dB SNDR 1 kHz BW multi-step incremental ADC using multi-slope extended counting with a single integrator.}, url = {http://dblp.uni-trier.de/db/conf/vlsic/vlsic2016.html#ZhangCHT16}, year = 2016 }