%0 Journal Article %1 journals/vlsi/AlexanderCGR98 %A Alexander, Michael J. %A Cohoon, James P. %A Ganley, Joseph L. %A Robins, Gabriel %D 1998 %J VLSI Design %K dblp %N 1 %P 97-110 %T Placement and Routing for Performance-Oriented FPGA Layout. %U http://dblp.uni-trier.de/db/journals/vlsi/vlsi7.html#AlexanderCGR98 %V 7

@article{journals/vlsi/AlexanderCGR98, added-at = {2023-05-08T00:00:00.000+0200}, author = {Alexander, Michael J. and Cohoon, James P. and Ganley, Joseph L. and Robins, Gabriel}, biburl = {https://www.bibsonomy.org/bibtex/2867d54490a48914d20b681a834413cdc/dblp}, ee = {https://doi.org/10.1155/1998/38483}, interhash = {c9328a1b926fedf844765a139400efb6}, intrahash = {867d54490a48914d20b681a834413cdc}, journal = {VLSI Design}, keywords = {dblp}, number = 1, pages = {97-110}, timestamp = {2024-04-08T12:07:25.000+0200}, title = {Placement and Routing for Performance-Oriented FPGA Layout.}, url = {http://dblp.uni-trier.de/db/journals/vlsi/vlsi7.html#AlexanderCGR98}, volume = 7, year = 1998 }