%0 Conference Paper %1 conf/asicon/LiLCW17 %A Li, Zhiwei %A Li, Yan %A Chen, Song %A Wu, Feng %B ASICON %D 2017 %E Qin, Yajie %E Hong, Zhiliang %E Tang, Ting-Ao %I IEEE %K dblp %P 237-240 %T A fully pipelined hardware architecture for convolutional neural network with low memory usage and DRAM bandwidth. %U http://dblp.uni-trier.de/db/conf/asicon/asicon2017.html#LiLCW17 %@ 978-1-5090-6625-4

@inproceedings{conf/asicon/LiLCW17, added-at = {2018-09-08T00:00:00.000+0200}, author = {Li, Zhiwei and Li, Yan and Chen, Song and Wu, Feng}, biburl = {https://www.bibsonomy.org/bibtex/234d2ef6315e130086e0cb81c073db7ec/dblp}, booktitle = {ASICON}, crossref = {conf/asicon/2017}, editor = {Qin, Yajie and Hong, Zhiliang and Tang, Ting-Ao}, ee = {https://doi.org/10.1109/ASICON.2017.8252456}, interhash = {d0c9ff83ea6a5c4a1f8a8210d34f7c33}, intrahash = {34d2ef6315e130086e0cb81c073db7ec}, isbn = {978-1-5090-6625-4}, keywords = {dblp}, pages = {237-240}, publisher = {IEEE}, timestamp = {2018-09-11T11:39:23.000+0200}, title = {A fully pipelined hardware architecture for convolutional neural network with low memory usage and DRAM bandwidth.}, url = {http://dblp.uni-trier.de/db/conf/asicon/asicon2017.html#LiLCW17}, year = 2017 }