%0 Conference Paper %1 conf/vlsid/ChanGG10 %A Chan, Tuck-Boon %A Ghaida, Rani S. %A Gupta, Puneet %B VLSI Design %D 2010 %I IEEE Computer Society %K dblp %P 423-428 %T Electrical Modeling of Lithographic Imperfections. %U http://dblp.uni-trier.de/db/conf/vlsid/vlsid2010.html#ChanGG10 %@ 978-0-7695-3928-7

@inproceedings{conf/vlsid/ChanGG10, added-at = {2023-03-24T00:00:00.000+0100}, author = {Chan, Tuck-Boon and Ghaida, Rani S. and Gupta, Puneet}, biburl = {https://www.bibsonomy.org/bibtex/23bf36fc8d8cca0625f4ecfa955d6ed23/dblp}, booktitle = {VLSI Design}, crossref = {conf/vlsid/2010}, ee = {https://doi.ieeecomputersociety.org/10.1109/VLSI.Design.2010.24}, interhash = {d105745754d99775410f366e7dd3dac7}, intrahash = {3bf36fc8d8cca0625f4ecfa955d6ed23}, isbn = {978-0-7695-3928-7}, keywords = {dblp}, pages = {423-428}, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T04:17:37.000+0200}, title = {Electrical Modeling of Lithographic Imperfections.}, url = {http://dblp.uni-trier.de/db/conf/vlsid/vlsid2010.html#ChanGG10}, year = 2010 }