%0 Thesis %1 wang2014analog %A Wang, Xiaoying %D 2014 %K %T Analog circuit design approaches

@phdthesis{wang2014analog, added-at = {2023-12-13T09:46:47.000+0100}, author = {Wang, Xiaoying}, biburl = {https://www.bibsonomy.org/bibtex/250d2bcacb7f46c719963c2b4596602db/admin}, dnbtitleid = {1053168586}, interhash = {d1b3266aa12ca0a90c57d4d618b633dd}, intrahash = {50d2bcacb7f46c719963c2b4596602db}, keywords = {}, school = {Uni Frankfurt Main}, timestamp = {2023-12-13T09:46:47.000+0100}, title = {Analog circuit design approaches}, year = 2014 }