%0 Conference Paper %1 conf/vlsic/0003STTLB20 %A Ding, Ming %A Song, Minyoung %A Tiurin, Evgenii %A Traferro, Stefano %A Liu, Yao-Hong %A Bachmann, Christian %B VLSI Circuits %D 2020 %I IEEE %K dblp %P 1-2 %T A 0.9pJ/Cycle 8ppm/°C DFLL-Based Wakeup Timer Enabled by a Time-Domain Trimming and An Embedded Temperature Sensing. %U http://dblp.uni-trier.de/db/conf/vlsic/vlsic2020.html#0003STTLB20 %@ 978-1-7281-9942-9

@inproceedings{conf/vlsic/0003STTLB20, added-at = {2022-10-02T00:00:00.000+0200}, author = {Ding, Ming and Song, Minyoung and Tiurin, Evgenii and Traferro, Stefano and Liu, Yao-Hong and Bachmann, Christian}, biburl = {https://www.bibsonomy.org/bibtex/23976afd3da5442281ef7a2ee3bb46911/dblp}, booktitle = {VLSI Circuits}, crossref = {conf/vlsic/2020}, ee = {https://doi.org/10.1109/VLSICircuits18222.2020.9162787}, interhash = {d88bfba5a50b9240e8e4deaf2cd3297d}, intrahash = {3976afd3da5442281ef7a2ee3bb46911}, isbn = {978-1-7281-9942-9}, keywords = {dblp}, pages = {1-2}, publisher = {IEEE}, timestamp = {2024-04-10T15:34:38.000+0200}, title = {A 0.9pJ/Cycle 8ppm/°C DFLL-Based Wakeup Timer Enabled by a Time-Domain Trimming and An Embedded Temperature Sensing.}, url = {http://dblp.uni-trier.de/db/conf/vlsic/vlsic2020.html#0003STTLB20}, year = 2020 }