%0 Journal Article %1 journals/tci/QasaimehSS15 %A Qasaimeh, Murad %A Sagahyroon, Assim %A Shanableh, Tamer %D 2015 %J IEEE Trans. Computational Imaging %K dblp %N 1 %P 56-70 %T FPGA-Based Parallel Hardware Architecture for Real-Time Image Classification. %U http://dblp.uni-trier.de/db/journals/tci/tci1.html#QasaimehSS15 %V 1

@article{journals/tci/QasaimehSS15, added-at = {2017-03-17T00:00:00.000+0100}, author = {Qasaimeh, Murad and Sagahyroon, Assim and Shanableh, Tamer}, biburl = {https://www.bibsonomy.org/bibtex/2306667a23878c42a7764a8ec5fb1231a/dblp}, ee = {http://dx.doi.org/10.1109/TCI.2015.2424077}, interhash = {e27e41206c9a6c07605d67e2723247e7}, intrahash = {306667a23878c42a7764a8ec5fb1231a}, journal = {IEEE Trans. Computational Imaging}, keywords = {dblp}, number = 1, pages = {56-70}, timestamp = {2017-03-18T11:34:42.000+0100}, title = {FPGA-Based Parallel Hardware Architecture for Real-Time Image Classification.}, url = {http://dblp.uni-trier.de/db/journals/tci/tci1.html#QasaimehSS15}, volume = 1, year = 2015 }