%0 Journal Article %1 journals/tvlsi/AgarwalPMDR05 %A Agarwal, Amit %A Paul, Bipul Chandra %A Mahmoodi-Meimand, Hamid %A Datta, Animesh %A Roy, Kaushik %D 2005 %J IEEE Trans. Very Large Scale Integr. Syst. %K dblp %N 1 %P 27-38 %T A process-tolerant cache architecture for improved yield in nanoscale technologies. %U http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi13.html#AgarwalPMDR05 %V 13

@article{journals/tvlsi/AgarwalPMDR05, added-at = {2020-10-26T00:00:00.000+0100}, author = {Agarwal, Amit and Paul, Bipul Chandra and Mahmoodi-Meimand, Hamid and Datta, Animesh and Roy, Kaushik}, biburl = {https://www.bibsonomy.org/bibtex/2d5044d7b8bc57d5f99b2fff648b2930c/dblp}, ee = {https://doi.org/10.1109/TVLSI.2004.840407}, interhash = {1ea762c83e1f8de5e4a5f613fc12dfda}, intrahash = {d5044d7b8bc57d5f99b2fff648b2930c}, journal = {IEEE Trans. Very Large Scale Integr. Syst.}, keywords = {dblp}, number = 1, pages = {27-38}, timestamp = {2020-10-27T11:55:34.000+0100}, title = {A process-tolerant cache architecture for improved yield in nanoscale technologies.}, url = {http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi13.html#AgarwalPMDR05}, volume = 13, year = 2005 }